The present invention relates to power supplies and in particular to voltage converters employing two controlled switches, one of which operates as a synchronous rectifier. The two switches are generally controlled so that both switches are never on at the same time. A “dead time” is provided between the on-times of the two switches to prevent cross conduction across the DC voltage supply between which the two switches are connected in series.
Synchronous rectification has been widely adopted for use in low voltage output converters of various topologies: buck, boost, flyback and forward. By substituting a MOSFET switch for a silicon or Schottky diode, rectification losses can be dramatically reduced. For synchronous converters, it is essential that a non-overlap period (dead time) be maintained in order to prevent cross conduction of the control switch with the synchronous rectifier switch. The power loss penalty for significant overlap is extremely high compared to the additional conduction losses occurring during dead time.
Still, dead time losses are significant, especially as converter operating frequency is increased. Using the example of a synchronous buck converter with the following characteristics:
Operating frequency=1 Mhz
Input voltage=12 volts
Output voltage=1 volt
Output current=40 amperes
Synchronous switch on resistance=3 mΩ
Synchronous switch body diode VF@ 40A=0.8V
Instantaneous power loss will be 4.8 watts with the FET on, but 32 watts with only the body diode conducting. With the above conditions, this translates into an additional 27 mW power loss per nanosecond of dead time. Two switching edges per cycle of 20 ns dead time each results in an additional 1.088 watts of loss in the synchronous switch, a 20% increase in losses for that component. Using a Schottky diode in parallel with the MOSFET will reduce that figure by 30% to 40%, but at additional cost and component count.
Additionally, once the body diode of the synchronous switch conducts, it is subject to a reverse recovery period and associated charge which must be swept out of the junction. This amounts to cross conduction and causes additional losses in the control FET.
The present invention seeks to minimize the power losses associated with dead time. This is accomplished by minimizing dead time to reduce body diode conduction losses, and in some cases, by allowing FET switch cross conduction to eliminate body diode conduction altogether, thus eliminating reverse recovery associated losses.
Methods have been employed in the past to attempt to minimize power losses associated with dead time. However, all of these methods have disadvantages. These methods include adjustable dead time, adaptive dead time and predictive dead time.
With the adjustable dead time method, dead time is adjusted at design so that cross conduction will be avoided under all operating conditions and over the full process variation of all components involved in achieving the dead time. Process variation of semiconductors can be significant and circuit operation may be over a wide range of operating conditions. Consequently, when no crossover is achieved with the worst case components at the worst case conditions, dead time with best case components and conditions is excessive. This results in excessive wasted power loss.
Adaptive dead time is an improvement over the above dead time method in that it can adjust on the fly as conditions change, and adapt to component variations. Essentially, it is a logic control whereby the gate of one switch is prevented from turning on, until the gate of the other switch has been detected to turn off. Superficially, this seems to solve the problem, but in practice it does not. Finite time periods are required for logic control, and for charging and discharging gates of the power switches themselves. In actual practice this results in dead times on the order of 10 ns-to-30 ns per switching transition for a total of 20 ns-to-60 ns per cycle.
Predictive dead time is the third prior art approach. Most of the problem with adaptive dead time is the time required to switch the FETs off and on. Predictive dead time solves that deficiency by using a phase locked loop or some other loop to reduce dead time until it is near zero. There appears to provide many of the same benefits as the present invention, but the use of a control loop has attendant disadvantages. Since this methodology relies on a control loop of some sort to set dead time, there is also an associated settling time in that loop. During transient conditions, cross conduction may occur while the loop tries to settle into a new steady state. If fixed dead time is programmed into the loop to avoid cross conduction, then most of the time there will be more than minimum dead time and associated losses. In any case, the loop solution relies on some arbitrary electrical conditions rather than minimizing the losses associated with dead time.